1. Field of the Invention
The present invention relates to methods and circuits for compensating the effect of switch resistance on settling time of high speed switched capacitor circuits.
2. Description of the Background Art
With the advent of MOS sub-micron technology circuits that function at low supply voltages, analog circuits must be implemented with minimal voltage headroom. An important class of analog circuits is based on the switched capacitor principle. These circuits include sample and hold circuits, track and hold circuits, switched capacitor amplifiers, switched capacitor filters, analog to digital converters (ADCs), chopper based circuits, and the like, and are used in most analog front-end solutions for mixed signal integrated circuits. In CMOS technology, such circuits are usually based on an interconnection of operational transconductance amplifiers (OTA) and capacitors by means of switches. Examples of conventional switched capacitor circuits can be found in Proceedings of the IEEE, xe2x80x9cSwitched-Capacitor Circuit Designxe2x80x9d by Gregorian et al. (vol. 71, no. 8, pp 941-966, August 1983) and Design of Analog Integrated Circuits by Laker et al. (McGraw Hill, 1994, p 810). The need to design these switched capacitor circuits and use all available speed from a certain technology leads to both OTA and switch optimization within the limited voltage budget.
One of the figures of merit for these discrete-time analog processing circuits is the output settling time within a predefined error. The value of the output settling time dictates or limits some of the most important performance figures of these circuits, such as sampling frequency, harmonic distortion, signal to noise and distortion ratio, effective number of bits, signal processing bandwidth, etc.
The on-resistance of the switches connected in series with the switched capacitors create parasitic poles that adversely impact the settling performance of these circuits. The low supply voltage (low gate overdrive voltage) leads to higher switch on-resistance and degrades settling performance. In order to reduce the on-resistance, larger width transistors can be used. However, such larger width transistors increase both parasitic capacitance and clock feed-through, thus degrading settling performance. There is therefore a need to compensate the adverse effect of switch resistance on settling time.
A conventional approach to the problem of reducing the adverse effects of switch resistance on settling time includes using NMOS transistor based switches that connect plates of the switched capacitors to lower voltage nodes, so that the voltage gate overdrive is large enough and constant. All remaining switches of the circuit are CMOS transistor based switches. The sizes of the various transistors are determined assuming that the bandwidth of the switches and the capacitors together is much higher than the bandwidth of the OTAs and the capacitors. When voltage and speed are not limiting factors, the sizes of the MOS transistors are kept to a minimum and are usually constant throughout the design.
For example, FIG. 1 illustrates a conventional switched-capacitor circuit including OTA 400 and NMOS transistors that couple plates of the circuit capacitors to lower voltage nodes, or the ground potential in this instance. The circuit includes capacitor 411 having a first plate that is coupled to the inverting input of OTA 400 and that is also coupled to a first end of NMOS transistor 403. Capacitor 411 also has a second plate that is coupled to a first end of NMOS transistor 401, wherein second ends of NMOS transistors 401 and 403 are coupled to system ground. The second end of NMOS transistor 403 is also coupled to the non-inverted input of OTA 400. The second plate of capacitor 411 is also coupled to a first end of CMOS switch 423, which is illustrated in greater detail in FIG. 1A. The second end of CMOS switch 423 is coupled to a previous stage of the switch-capacitor circuit that is not illustrated.
The conventional switched-capacitor circuit of FIG. 1 further includes CMOS switch 425 having a first end that is coupled to the output of OTA 400 and a second end that is coupled to a first plate of capacitor 413. NMOS switch 405 has a first end that is coupled to the first plate of capacitor 413 and a second end that is coupled to system ground. A second plate of capacitor 413 is coupled to the inverting input of OTA 400, to complete a feedback path.
As further illustrated in FIG. 1, the next stage of the switched-capacitor circuit includes CMOS switch 427 having a first end that is coupled to the output of OTA 400 and having a second end that is coupled to a first plate of capacitor 415. NMOS switch 407 includes a first end that is coupled to a second plate of capacitor 415 and includes a second end that is coupled to system ground. The gates of NMOS transistors 401, 403, 405 and 407 and the gates of CMOS switches 423, 425 and 427 are typically driven by a control circuit that is not illustrated in FIG. 1. A primary disadvantage of a switched-capacitor circuit of this type is that the circuit is not appropriate for high speed operation due to large parasitic capacitance that is added to the circuit nodes by the CMOS switches.
If the relatively slower speed of the conventional circuit as described with respect to FIG. 1 can not be tolerated, the extra capacitance added by the slow and large PMOS transistors of CMOS switches 423, 425 and 427 and the extra capacitance added by the interconnect capacitance of the CMOS switches, must be reduced. Thus, a second conventional approach comprises eliminating the PMOS transistors of CMOS switches 423, 425, and 427 of the FIG. 1 circuit. The CMOS switches are respectively replaced with NMOS transistors 417, 419 and 421 as illustrated in FIG. 2, such that the circuit includes only NMOS transistor switches. Specifically, the circuit of FIG. 2 is configured the same as the circuit of FIG. 1, except for NMOS transistor 417 that includes a first end that is coupled to the second plate of capacitor 411 and a second end that is coupled to the previous stage, NMOS transistor 419 that includes a first end that is coupled to the output of OTA 400 and a second end that is coupled to the first plate of capacitor 413, and NMOS transistor 421 that includes a first end that is coupled to the output of OTA 400 and a second end that is coupled to the first plate of capacitor 415.
The approach of the FIG. 2 circuit has the advantage that only fast NMOS transistors are used for switches. However, a primary disadvantage of this approach is that the dynamic range of the circuit is reduced. Moreover, the sizes of the MOS transistors are determined by keeping the switch bandwidth much higher than the OTA bandwidth. As a result, the sizes of the switches must necessarily be large, so that even at high input or output voltages (low switch gate overdrive voltage), the switch bandwidth is much higher than the OTA bandwidth. This approach leads to a much tighter compromise between the dynamic range at the output of the circuit and the settling time at the output of the circuit.
To overcome the above-noted problems of the conventional all-NMOS switch circuit as illustrated in FIG. 2, the gate overdrive voltage for the switch transistors can be increased by means of an on-chip voltage multiplier. There are two conventional alternatives to this approach. In a first alternative as illustrated in FIG. 3, voltage multiplier 431 and level shifters 433 are implemented to ensure that the switch control voltage of the NMOS switches are constant and higher than the supply voltage Vdd. The circuit of FIG. 3 is configured the same as the circuit of FIG. 2, except for level shifters 433 that drive the gates of NMOS transistors 401, 403, 405, 417 and 419, and except for voltage multiplier 431 which multiples supply voltage Vdd and provides the higher multiplied voltage to level shifters 433.
According to a second alternative as illustrated in FIG. 4, charge pump circuits 441 and 442 are implemented so that the switch control voltage follows the switched node voltage (i.e. the switch gate overdrive voltage has a large and constant value). The circuit of FIG. 4 is configured the same as the circuit of FIG. 2, except for charge pump circuit 442 that is coupled to the output of OTA 400 and that provides the switch gate overdrive voltage to NMOS transistor 419, and except for charge pump circuit 441 that is coupled to the second end of NMOS transistor 417 and that provides the switch gate overdrive voltage to NMOS transistor 417. However, the voltage multiplier approaches as exemplified in FIGS. 3 and 4 have disadvantages which include increasing circuit area, increasing power requirements particularly in view of the charge pumps, and potentially reducing production yield due to higher on-chip voltages. Also, the charge pumps and voltage multipliers contribute to an increase in injected switching noise.
A still further conventional approach useful for very low supply voltage is based on the observation that the high swing nodes are usually at the output of the OTAs. Instead of using switches at the output in series with capacitors, the switched OP-AMP approach is based on using circuit topologies that allow for cutting the output stage of the OTA and short-circuiting this node to ground, as illustrated in FIG. 5. Specifically, using similar elements and notations as in FIG. 2 for simplicity of description, the conventional circuit of FIG. 5 includes OTA 400, NMOS transistor 403, and capacitors 411 and 413 configured as previously. However, the first end of capacitor 413 is directly coupled to the output of OTA 400, and NMOS transistor 419 and the remaining elements of FIG. 2 not specifically mentioned are not implemented in the circuit of FIG. 5. NMOS transistor 429 includes a first end that is coupled to the output of OTA 400 and a second end that is coupled to ground, and NMOS transistor 429 serves to short-circuit the output stage of OTA 400 to ground.
This solution as described with respect to FIG. 5 has the advantage of eliminating the output series switch that is a limiting factor for a large class of switched capacitor circuits. However, the switched OP-AMP approach is mainly targeted for very low supply voltages and lower speed. This is due to the fact that the whole OTA output stage is switched, including transistors with high current density. This operation can take a long period of time because a large stored charge needs to be eliminated during on to off switching of the circuit.
The present invention is therefore directed to a circuit and method for improving settling of switched-capacitor circuits, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above noted problems, it is an object of the present invention to provide a circuit including an operational transconductance amplifier having an input terminal and an output terminal, the operational transconductance amplifier amplifies a signal provided at the input terminal and provides an amplified signal at the output terminal; a feedback section that provides a feedback signal to the input terminal based on the amplified signal, the feedback section including a first switched capacitor and having a first time constant; and a load section that provides the amplified signal as an output of the circuit, the load section including a second switched capacitor and having a second time constant, the first time constant matching the second time constant to improve settling of the circuit.
In a preferred embodiment, the first and second switched capacitors are coupled to the output terminal of the operational transconductance amplifier by respective transistors, wherein channel widths and lengths of the transistors are sized so that the first time constant and the second time constant are matched. In a further preferred embodiment, the transistors are NMOS transistors.
It is a further object of the present invention to provide a method of improving settling of a circuit including an operational transconductance amplifier, a feedback stage having a first switched capacitor and a load stage having a second switched capacitor, the method including matching a time constant of the feedback stage and a time constant of the load stage.
In a preferred embodiment of the method of improving settling, the first and second switched capacitors are coupled to an output of the operational transconductance amplifier by respective transistors, wherein the matching comprises providing the transistors as having channel widths and lengths that are sized so that the first and second time constants are matched. In a further preferred embodiment, the transistors are NMOS transistors.
It is a still further object of the present invention to provide a circuit comprising an operational transconductance amplifier, a feedback section and a load section, wherein the first time constant of the feedback section is greater than the second time constant of the load section, to improve settling of the circuit. In a preferred embodiment of the circuit, resistance of the transistors in an on-state is controlled based on transconductance of the operational transconductance amplifier. In a still further preferred embodiment the transistors are NMOS transistors.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.